1. Field of the Invention
The present invention relates to an input/output (I/O) circuit which is capable of providing tri-state outputs and, particularly, to an I/O circuit which performs a pull-down/pull-up operation when a high impedance is output, and to a control method for controlling the I/O circuit.
2. Description of the Related Art
A known circuit configuration is shown in FIG. 7 or FIG. 8 comprising a conventional I/O circuit for providing tri-state outputs.
An I/O circuit shown in FIG. 7 outputs three states of low level, high level or high impedance state to an I/O terminal 103 by controlling an output buffer 100. The output buffer 100 comprises a P-channel Field Effect Transistor (FET) and an N-channel FET directly connected to each other in series between a high level power source S and a low level power source (for example, ground) G by an output control circuit 102. The output control circuit 102 comprises one or more logic gates (for example, logic circuits shown in FIG. 7) operating with a signal provided to output control terminals 101. The I/O circuit receives an input signal provided from, for instance, a bus connected to the I/O terminal 103 to an internal circuit via a protective resistor 107 and an input buffer 104. Further, a pull-down resistor 105 is connected to the I/O terminal 103 of the I/O circuit to pull it down to ground potential when the I/O terminal 103 becomes the high impedance state.
In the I/O circuit in such a structure, when a high level signal is provided to the I/O terminal 103, the current continues to flow to the ground G from the I/O terminal 103 via the protective resistor 107 and the pull-down resistor 105. Although the amount of the current decreases if this pull-down resistor 105 is has high resistance value, the current still continues to flow a little. Therefore, the power consumption increases and with the increase of the number of I/O circuits, the increase in power consumption becomes remarkable. Further, when the pull-down resistor 105 is integrated to have a high resistance, a large space is required for forming the integrated resistors on the semiconductor chip, resulting in a drop in the degree of integration.
An I/O circuit shown in FIG. 8 connects a pull-up resistor 106 to the I/O terminal 103 which pulls up the I/O terminal 103 to a high level power source S when the I/O terminal 103 becomes the high impedance state. The rest of the structure is the same as that shown in FIG. 7.
In such a structure, when a low level signal is provided to the I/O terminal 103, the current flows continuously to the I/O terminal 103 from the high level power source S via the protective resistor 107 and the pull-up resistor 106. If this pull-up resistor 106 is at a sufficiently high resistance value, the amount of current decreases, but current still continues to flow. Therefore, the same problem as that in the I/O circuit shown in FIG. 7 also arises in this I/O circuit.
There is also an I/O circuit (not shown) in which an N-channel FET is applied as a pull-down means instead of the pull-down resistor 105 shown in FIG. 7. The N-channel FET is switched by a control signal that controls the output buffer 100 and this FET is turned on only when the I/O circuit 103 becomes the high impedance state. Even in this structure, when a high level signal is provided to the I/O circuit 103 and the I/O terminal 103 becomes the high impedance state, the current flows in the N-channel FET the same as in the pull-down resistor 105 in FIG. 7. Thus, the power consumption will increase. Also, the same problem exists in a structure wherein, for instance, a P-channel FET which is switched by a control signal that controls the output buffer 100 is applied as a pull-up means instead of the pull-up resistor 106 shown in FIG. 8 so as to turn this FET on only when the I/O terminal 103 becomes the high impedance state.
As described above, in a conventional I/O circuit which performs the pull-down/pull-up operation, when a low level or high level signal is provided to an I/O terminal, the current flows continuously between the I/O terminal and a low level or high level power source through a structure to perform pull-down or pull-up operation, namely the N-channel FET and the P-channel FET. Therefore, an increase in the power consumption in I/O circuits of the prior art cannot be avoided.